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BARZAGHI M.

Last name: BARZAGHI M.

1991 (v1)

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Transputer Application for Integrated Circuit Layout Verification

CHIRICO M. CAVIGLIA, DANIELE BARZAGHI M.

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Uploaded on: December 5, 2022
1990 (v1)

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An Algorithm for the Definition of Routing Regions in VLSI Design

CURATELLI, FRANCESCO BISIO G. M CAVIGLIA, DANIELE

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Uploaded on: December 4, 2022
1991 (v1)

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Implementation of an efficient algorithm for VLSI design rule checking on a 2-D mesh of transputers

CAVIGLIA, DANIELE CURATELLI, FRANCESCO BISIO, GIACOMO

A design rule checking program for VLSI circuit layouts with Manhattan geometries is presented. The layout model is described along with the way the authors implemented the check through few and simple primitives for describing parameteric rules. A single main function for the geometrical test is outlined and how the authors succeeded in...

Uploaded on: April 14, 2023
1992 (v1)

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A Parallel Approach to Symbolic Layout Compaction of Digital CMOS Cells

BARZAGHI M. CAVIGLIA, DANIELE CHIRICO M.

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Uploaded on: December 5, 2022