FERNÁNDEZ FERNÁNDEZ , Francisco Vidal

Symbolic analysis potentialities for gaining circuit insight and for efficient repetitive evaluations have been limited by the exponential increase of formula complexity with the circuit size. This drawback has began to be solved by the introduction of simplification before and during generation techniques. An appropriate error control in both...

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This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state of the art in this field is also studied, pointing out directions for future research.

In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and response-surface-based yield optimization methods face challenges in accuracy. Monte-Carlo (MC) simulation is general and accurate for yield estimation, but its efficiency is not high enough to make MC-based analog yield optimization, which requires...

This paper presents two approaches to symbolic analysis of large analog integrated circuits via simplification during the generation of the symbolic expressions. Both techniques are examined from the point of view of matroid theory. Finally, a new approach which combines the positive features of both approaches is introduced.

Welcome to the Special Issue devoted to the 2012 edition of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). This is the XIIth edition of the conference, and it was held on 19–21 September 2012 in Seville, Spain. SMACD originated from a specialized workshop in 1991...

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design...

Behavioral models are used both for top-down design and for bottom-up verification. During top-down design, models are created that reflect the nominal behavior of the different analog functions, as well as the constraints imposed by the parasitics. In this scenario, the availability of symbolic modeling expressions enable designers to get...

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a...

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD...

This paper presents an analytical approach to distance term compensation in mismatch models of integrated devices. Firstly, the conditions that minimize parameter mismatch are examined under the assumption of zero-area devices. The analytical developments are illustrated using centroid configurations. Then, deviations from the previous approach...

A tool for symbolic analysis of analog integrated circuits is presented featuring accurate simplification, pole/zero extraction, and tools for parametric AC circuit characterization. The program, called ASAP, uses signal flowgraph methods and has been written in C for portability. In its current version, ASAP is able to deal with the complexity...