G. M. BO

An analog VLSI neural network integrated circuit is presented. It consist of a feedforward multi layer perceptron (MLP) network with 64 inputs, 64 hidden neurons and 10 outputs. The computational cells have been designed by using the current mode approach and weak inversion biased MOS transistors to reduce the occupied area and power...

The classification of handwritten digits through an analog feature extractor chip and neural classifier is discussed in this paper. The chip implements a feature extraction algorithm onto analog circuits; it extracts a set of 112 features from the input character (32 x 24 binary pixel matrix). The features, coded by current signals, are given...

Low-power, high efficiency, small size and real-time optical character recognition (OCR) systems can benefit from the analog VLSI implementation of (at least) some of their constituting modules. The reference architecture usually consists of a feature detection and extraction block (FE) directly interfaced to the on-chip CMOS sensor, and of a...

In this paper we present the analog CMOS design of a multi-layer-perceptron network with on-chip by-pattern back-propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient in terms of convergence speed. Circuit simulation results validate the network behavior