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Last name: RÍO FERNÁNDEZ
First name: Rocío Del
El trabajo desarrollado en esta Tesis pretende demostrar la viabilidad de implementar de forma robusta convertidores sigma-delta de alta velocidad y alta resolución utilizando tecnologías CMOS profundamente submicrométricas orientadas al desarrollo de sis
Privacy awareness constitutes a critical aspect for smart camera networks. An ideal awless protection of sensitive information would boost their application scenarios. How- ever, it is still far from being achieved. Numerous chal- lenges arise at di erent levels, from hardware security to subjective perception. Generally speaking, it can be...
A single-exposure technique to extend the dynamic range of vision sensors is presented. It is particularly suitable for vision algorithms requiring region-of-interest (ROI) tracking under varying illumination conditions. The operation is supported by two intertwined photo-diodes at pixel level and two digital registers at the periphery of the...
Focal-plane mixed-signal arrays have traditionally been designed according to the general claim that moderate accuracy in processing is affordable. The performance of their circuitry has been analyzed in these terms without a comprehensive study of the ultimate consequences of such moderate accuracy. In this paper, for the first time to the...
La Electrónica es una disciplina versátil en cuanto a las metodologías y técnicas docentes que pueden emplearse. Frente a las clases magistrales, experiencias de cátedra, tutorías y clases prácticas, el Trabajo Académicamente Dirigido (TAD) se muestra como altamente eficiente a la hora de trasvasar conocimiento al alumno. En esta comunicación...
This paper studies the effects of capacitors non-idealities in the performance of un-even split-capacitor SAR ADCs. Also, election of the m and l bits of MSB and LSB capacitors banks, respectively, is studied to reduce SAR errors.To exemplify and quantify the non-idealities, MOM capacitors are used. In particular, MOM layout parasitics and...
The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5pA) and high-speed for low input currents (8ns at 50nA). The new structure features a speed improvement of more than two orders of magnitude for a 1 nA input current, when compared to the fastest reported to date.
This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current...
This paper explores the use of /spl Sigma//spl Delta/ modulators for A/D conversion in xDSL applications. Two high-order multibit architectures, the 2-1-1mb modulator and a novel 2-1-1-1mb cascade (MASH), are proposed to achieve 14 bit dynamic range@4.4 MS/s using low oversampling ratio. They show very low sensitivity to the internal DAC...
CMOS Single Photon Avalanche Diodes (SPADs) are a dedicated type of photodetectors that are attracting increasing interest. Crosstalk and fill factor are magnitudes that become important when dealing with arrays of SPADs. There are trade-offs that involve these two magnitudes and dark count rate (DCR) which are of great interest for the...
The use of Sigma-Delta (Σ∆) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC)...
This paper presents a detailed study on the transient response of SC integrators which takes into account the effects of amplifier finite gain-bandwidth product, slew-rate, and parasitic capacitances. Unlike previous models, both the integration and the sampling phases are considered. Experimental measurements of the settling error power of a...
Recommendations are given for efficient design of high-frequency /spl Sigma//spl Delta/ modulators using multi-stage (cascade) multi-bit quantization architectures. These cover from pure architectural aspects to cell design with special emphasis on the impact of circuit imperfections. Conclusions are validated by measurements on a 13-bit 2.2...
This paper describes a prototype smart imager capable of adjusting the photo-integration time of multiple regions of interest concurrently, automatically and asynchronously with a single exposure period. The operation is supported by two interwined photo-diodes at pixel level and two digital registers at the periphery of the pixel matrix. These...
Privacy concerns are hindering the introduction of smart camera networks in prospective application scenarios like retail analytics, factory monitoring or elderly care. The idea of networked cameras pervasively collecting data gen- erates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate...
The capture, processing and distribution of visual information is one of the major challenges for the paradigm of the Internet of Things. Privacy emerges as a fundamental barrier to overcome. The idea of networked image sensors pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers...
This paper presents the design and implementation of a fourth-order band-pass continuous-time modulator intended for the digitization of radio-frequency signals in softwaredefined- radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in...
This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multistandard wireless terminals, covering three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuitlevel in order to adapt its performance to the different standard specifications with optimized power consumption. The design...
This paper presents innovative architectures of hybrid Continuous-Time/Discrete-Time (CT/DT) cascade ΣΔ Modulators (ΣΔMs) made up of a front-end CT stage and a back-end DT stage. In addition to increasing the digitized signal bandwidth as compared to conventional ΣΔMs, the proposed topologies take advantage of the CT nature of the front-end ΣΔM...