ROCA MORENO , Elisenda

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A chip designed in a 0.18 μm CMOS Image Sensor Technology (CIS) is presented which incorporates different pixel design alternatives for Active Pixel Sensor (APS). CIS technology improves characteristics such as sensitivity, dark current and noise, that are strongly layout dependent. This chip includes a set of pixel architectures where...

In this paper a general method for the determination of the series inductance of polygonal tapered inductors is presented. The value obtained can be integrated into any integrated inductor lumped element model, thus granting the overall characterization of the device and the evaluation of performance parameters such as the quality factor or the...

Welcome to the Special Issue devoted to the 2012 edition of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). This is the XIIth edition of the conference, and it was held on 19–21 September 2012 in Seville, Spain. SMACD originated from a specialized workshop in 1991...

This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors due to its very limited computing requirements since only local memories and a comparator are required at the pixel level. The presented algorithm employs measurements during exposure time to create a 4-bit...

Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not straightforward, neither it is to simulate the resulting circuit. The structure of these systems leads to a netlist of more than 100.000 nodes for a small array of 100×150 pixels. Moreover, introducing an optical input in the...

The use of Pareto-optimal performance fronts in emerging design methodologies for analog integrated circuits is a keystone to overcome the limitations of traditional design methodologies. However, most techniques to generate the fronts reported so far neglect the effect that the surrounding circuitry (such as the load impedance) has on the...

This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors (FPP) due to its very limited computing requirements since only local memories, little digital control and a comparator are required at the pixel level. The presented algorithm employs measurements during exposure...

Abstract—In emerging design methodologies for analog integrated circuits, the use of performance trade-off fronts, also known as Pareto fronts, is a keystone to overcome the limitations of the traditional top-down methodologies. However, most techniques reported so far to generate the front neglect the effect of the surrounding circuitry (such...

This paper introduces a new hierarchical analysis methodology which incorporates approximation strategies during the analysis process. Consequently, the circuit sizes that can be analyzed increase dramatically, without suffering from the combinatorial explosion of expression complexity. Moreover, the interpretability and usability in practical...

The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in tele-presence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide can be managed with many image processing algorithms to extract the required information. However, as in the case of vision...

The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in telepresence, minimal invasive surgery, robotics etc. The array of pressure data provided by these devices can be treated with different image processing algorithms to extract the required information. However, as in the case of...

From the point of view of mixed-mode scattering parameters, Smm, a two-port device can be excited using different driving conditions. Each condition leads to a particular set of input reflection and input impedance coefficient definitions that should be carefully applied depending on the type of excitation and symmetry of the two-port device....

Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, the design of general purpose, programmable CNN chips with dimensions required for practical applications raises many...

Abstract—An electrooptical measurement system for the dc characterization of visible detectors for CMOS-compatible vision chips is presented, which can help designers to characterize these detectors. The measurement system has been designed to be versatile, fast, and easily expandable and used. Two different setups for the measurement of the...

This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35μm n-well CMOS technology with one poly layer and five metal layers. It contains a digital shell for control and data interchange, and a central array of 128 × 128 identical cells,...

This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural net) chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as well as the mechanism for transducing the photogenerated charges into the correspondent pixel voltage. Both linear or...

The use of simplification before generation techniques to enable the approximate symbolic analysis of large analog circuits is discussed. This paper introduces an error control mechanism to drive the circuit reduction, which overcomes the accuracy problems of previous approaches. The features and efficiency of the new methodology are...

Nowadays, parametric macromodeling techniques are widely used to describe electromagnetic structures. In this contribution, the application of such parametric macromodeling techniques to the design of integrated inductors and radio-frequency circuit design is investigated. In order to allow such different operations, a new modeling methodology...

Circuit reduction is a fundamental first step in addressing the symbolic analysis of large analogue circuits. A new algorithm for simplification before generation is presented which is very efficient in terms of speed and the amount of circuit reduction, and solves the accuracy problems of previously reported approaches.

Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit...

In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators that were designed using a fully-automated, layout- and variability-aware optimization-based methodology. The methodology uses a highly accurate model, based on machine-learning techniques, to characterize inductors, and a...