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February 7, 2022 (v1)PublicationUploaded on: March 25, 2023
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May 28, 2018 (v1)Publication
En esta ponencia-demo se presenta una práctica donde se analiza la influencia en el tiempo de ejecución de algunas optimizaciones sobre el código máquina para procesadores reales (familia Intel Pentium). Se propone el estudio del efecto del emparejamiento de instrucciones y de las dependencias entre registros, la aceleración obtenida con el...
Uploaded on: March 27, 2023 -
February 7, 2022 (v1)Publication
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Uploaded on: March 25, 2023 -
December 20, 2019 (v1)Publication
Address-Event-Representation (AER) is a communication protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them in real time, while performing some processing. To develop and test AER based systems it is convenient to have a set of...
Uploaded on: March 25, 2023 -
February 4, 2022 (v1)Publication
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Uploaded on: March 27, 2023 -
February 4, 2022 (v1)Publication
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Uploaded on: March 27, 2023 -
May 14, 2018 (v1)Publication
Address event representation (AER) is a neuromorphic interchip communication protocol that allows for real-time connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (nano-seconds), synaptic neural connections can be time multiplexed (mili-seconds). When building multi-chip...
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July 5, 2017 (v1)Publication
Con la adaptación del Espacio Europeo de Educación Superior (EEES) y la creación de los nuevo títulos de grado, se plantea una nueva visión metodológica en la enseñanzas superiores. En el caso de titulaciones relativas a las ingenierías informáticas y electrónicas resulta muy interesante el uso de metodologías orientadas al Aprendizaje Basado...
Uploaded on: March 24, 2023