International audience
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2009 (v1)Book sectionUploaded on: December 2, 2022
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2006 (v1)Report
Design of real-time embedded systems requires particular attention to the careful scheduling of application onto execution platform. Precise cycle allocation is often requested to obtain full communication and computation throughput. Our objective is to provide a UML profile where events, actions, and objects can be annotated by ``logical''...
Uploaded on: December 3, 2022 -
October 12, 2009 (v1)Conference paper
An important step in model-based embedded system design consists in mapping functional specifications and their tasks/operations onto execution architectures and their resources. This mapping comprises both temporal scheduling and spatial allocation aspects. Therefore, we promote an approach which starts from loosely-timed/asynchronous models...
Uploaded on: December 4, 2022 -
March 2011 (v1)Report
We present a new technique for the concurrent asynchronous/GALS implementation of polychronous specifications. We start from programs written in multi-clock languages such as Signal/Polychrony or Esterel. We provide compact data structures and corresponding algorithms for program analysis, following the theory of weakly endochronous systems....
Uploaded on: December 3, 2022 -
October 2013 (v1)Journal article
Architecture analysis & design language (AADL) has been increasingly adopted in the design of embedded systems, and corresponding scheduling and formal verification have been well studied. However, little work takes code distribution and architecture exploration into account, particularly considering clock constraints, for distributed...
Uploaded on: December 3, 2022 -
October 2013 (v1)Journal article
Architecture analysis & design language (AADL) has been increasingly adopted in the design of embedded systems, and corresponding scheduling and formal verification have been well studied. However, little work takes code distribution and architecture exploration into account, particularly considering clock constraints, for distributed...
Uploaded on: October 11, 2023 -
May 2010 (v1)Conference paper
The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a broadly expressive Time Model to provide a generic timed interpretation for UML models. As a part of MARTE, Clock Constraint Specification Language (CCSL) allows the specification of systems with multiple clock domains as well as nondeterminism. In...
Uploaded on: December 4, 2022