W

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WILKE , G.

Last name: WILKE

First name: G.

January 20, 2017 (v1)

Publication

Metadata-only

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits

Guerrero Martos, David Wilke, G. Güntzel, J.L.

The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. A key factor in timing analysis is the election of the delay model type. Pin-to-pin delay models are usually employed, but their application is limited in timing analysis...

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