ZHU , Huibiao

MARTE (abbreviated for Modeling and Analysis of Real-Time and Embedded systems) is a UML profile which provides a generalmodeling framework to design and analyze real-time embedded systems. CCSL (abbreviated for Clock Constraint Specification Language) is aformal language companion to MARTE, used to specify the constraints between the...

The Clock Constraint Specification Language (CCSL) is a clock-based formalism for formal specification and analysis of real-time embedded systems. Previous approaches for the schedulability analysis of CCSL specifications are mainly based on model checking or SMT-checking. In this paper we propose a logical approach mainly based on theorem...

The Clock Constraint Specification Language (CCSL) is a clock-based formalism for the specification and analysis of real-time embedded systems. The major goal of schedulability analysis of CCSL specifications is to solve the schedule problem, which is to answer 'whether there exists a clock behaviour (also called a 'schedule') that conforms to...