International audience
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October 3, 2005 (v1)Conference paperUploaded on: October 11, 2023
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2007 (v1)Journal article
International audience
Uploaded on: February 28, 2023 -
June 11, 2006 (v1)Conference paper
International audience
Uploaded on: October 11, 2023 -
June 11, 2006 (v1)Conference paper
International audience
Uploaded on: December 2, 2022 -
June 19, 2005 (v1)Conference paper
International audience
Uploaded on: October 11, 2023 -
October 3, 2005 (v1)Conference paper
International audience
Uploaded on: December 3, 2022 -
June 19, 2005 (v1)Conference paper
International audience
Uploaded on: December 3, 2022 -
December 11, 2005 (v1)Conference paper
The aim of this study is to provide a high-level VHDL-AMS model for multi-standard phase locked loop in SOI technology. The supported standards are GSM, GPS, DCS, Bluetooth, Wifi and WLAN. The model can be used to evaluate settling times, channel-to-channel transition times and also the timing needed to switch from one standard to another one....
Uploaded on: December 3, 2022 -
October 6, 2004 (v1)Conference paper
National audience
Uploaded on: December 3, 2022 -
October 6, 2004 (v1)Conference paper
National audience
Uploaded on: October 11, 2023 -
December 11, 2005 (v1)Conference paper
The aim of this study is to provide a high-level VHDL-AMS model for multi-standard phase locked loop in SOI technology. The supported standards are GSM, GPS, DCS, Bluetooth, Wifi and WLAN. The model can be used to evaluate settling times, channel-to-channel transition times and also the timing needed to switch from one standard to another one....
Uploaded on: October 11, 2023 -
2008 (v1)Journal article
This paper deals with the design of a fractional PLL for wireless multi-standard applications. This circuit has been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. Five standards are covered by this structure: GSM (900 MHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11a (5.8...
Uploaded on: December 3, 2022 -
October 6, 2019 (v1)Conference paper
Analog integrated circuits, in particular passive components, never follow the Moore's law. FDSOI (Fully Depleted Silicon On Insulator) technology allows to reduce the SCE (Short Channel Effect) and to design new mixed-signal topologies in order to remove passive component. To illustrate this SCE problem, a current mirror was chosen and a new...
Uploaded on: January 13, 2025