Model-checking process equivalences
- Others:
- Laboratoire d'Informatique, Signaux, et Systèmes de Sophia Antipolis (I3S) ; Université Nice Sophia Antipolis (1965 - 2019) (UNS) ; COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-Centre National de la Recherche Scientifique (CNRS)-Université Côte d'Azur (UCA)
- Laboratoire Spécification et Vérification [Cachan] (LSV) ; École normale supérieure - Cachan (ENS Cachan)-Centre National de la Recherche Scientifique (CNRS)
Description
Process equivalences are formal methods that relate programs and systems which, informally, behave in the same way. Since there is no unique notion of what it means for two dynamic systems to display the same behaviour there are a multitude of formal process equivalences, ranging from bisimulation to trace equivalence, categorised in the linear-time branching-time spectrum. We present a logical framework based on an expressive modal fixpoint logic which is capable of defining many process equivalence relations: for each such equivalence there is a fixed formula which is satisfied by a pair of processes if and only if they are equivalent with respect to this relation. We explain how to do model checking for this logic in EXPTIME. This allows model checking technology to be used for process equivalence checking. We introduce two fragments of the logic for which it is possible to do model-checking in PTIME and PSPACE respectively, and show that the formulas that define the process equivalences we consider are in one of these fragments. This yields a generic proof technique for establishing the complexities of these process equivalences. Finally, we show how partial evaluation can be used to obtain decision procedures for process equivalences from the generic model checking scheme.
Abstract
International audience
Additional details
- URL
- https://hal.archives-ouvertes.fr/hal-01905142
- URN
- urn:oai:HAL:hal-01905142v1
- Origin repository
- UNICA