A processing element architecture for high-density focal plane analog programmable array processors

Description

The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 × 3 convolution masks. The vision chip has been implemented in a standard 0.35μm CMOS technology. The main PE related figures are: 180 cells/mm2, 18 MOPS/cell, and 180 μW/cell.

Abstract

Office of Naval Research (USA) N68171-98-C-9004

Abstract

Euopean Union IST-1999-19007

Abstract

Comisión Interministerial de Ciencia y Tecnología TIC1 999-0826

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