Published December 10, 2019
| Version v1
Publication
FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration
Description
In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA. The proposed RAM specification has been tested with different target devices.
Abstract
Ministerio de Educación y Ciencia TEC2006-11730-C03-02
Additional details
- URL
- https://idus.us.es/handle//11441/90787
- URN
- urn:oai:idus.us.es:11441/90787
- Origin repository
- USE