Power Modeling and Exploration of Dynamically Reconfigurable Multicore Designs

Description

This paper exhaustively explores the potential energy efficiency improvements of Dynamic and Partial Reconfiguration (DPR) on the concrete implementation of a H.264/AVC video decoder. The methodology used to explore the different implementations is presented and formalized. This formalization is based on pragmatic power consumption models of all the tasks of the application that are derived from real measurements. Results allow to identify low energy / high performance mappings, and by extension, conditions at which partial reconfiguration can achieve energy efficient application processing. The improvements are expected to be of 57% (energy) and 37% (performance) over pure software execution, corresponding also to 16% energy savings over static implementation of the same accelerators for 10% less performance.

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