Published May 31, 2023 | Version v1
Publication

On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter

Description

This paper describes a BIST technique for the static linearity test of Vcm-based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the Vcm-based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.

Additional details

Identifiers

URL
https://idus.us.es/handle//11441/146829
URN
urn:oai:idus.us.es:11441/146829