Published November 30, 2015 | Version v1
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Signal Sampling Based Transition Modeling for Digital Gates Characterization

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Description

Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%.

Abstract

Es una ponencia del Congreso: PATMOS 2004 : 14th International Workshop on Power and Timing Modeling, Optimization and Simulation. ISBN: 978-3-540-23095-3

Abstract

Ministerio de Ciencia y Tecnología VERDI TIC 2002-2283

Abstract

Ministerio de Educación, Cultura y Deporte / Secretaría de Estado de Educación y Universidades / Dirección General de Universidades PHB2002-0018-PC

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https://idus.us.es/handle/11441/31227
URN
urn:oai:idus.us.es:11441/31227

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