Efficient Design of a FFT/IFFT-64 Module on ASIC

Description

In this work we present the VHDL implementation of a FFT/IFFT-64 module. This implementation: (a) is relatively quick and (b) occupies a limited amount of area. The module operation is based on a radix-8 butterfly and it allows the calculation of a complex 64-element FFT/IFFT in 290 clock cycles providing a precision of 98.8% on the magnitude of the output samples. Area saving is achieved mainly by using a RAM macrocell in order to store intermediate calculations. The synthesis process has been carried out on ASIC using AMS 0.35 μm technology and reaching the place & routing level in the test process.

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