Spikes Monitors for FPGAs, an Experimental Comparative Study

In this paper we present and analyze two VHDL components for monitoring internal activity of spikes fired by silicon neurons inside FPGAs. These spikes monitors encode each spike according to the Address-Event Representation, sending them through a time multiplexed digital bus as discrete events, using different strategies. In order to study and analyze their behavior we have designed an experimental scenario, where diverse AER systems have been used to stimulate the spikes monitors and collect the output AER events, for later analysis. We have applied a battery of tests on both monitors in order to measure diverse features such as maximum spike load and AER event loss due to collisions.