Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems

Description

Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging "neural spikes" among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical wires together with a pair of handshaking signals (Request and Acknowledge). Here we present a fully serial implementation using bidirectional SATA connectors with a pair of LVDS (low voltage differential signaling) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links per LVDS physical connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs reaching a maximum event transmission speed of 75Meps (Mega Events per second) for 32-bit events at 3.0Gbps line data rate.

Abstract

Ministerio de Economía y Competitividad TEC2012-37868-C04-01

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Ministerio de Economía y Competitividad TEC2015-63884-C2-1-P

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Ministerio de Economía y Competitividad TEC2016-77785-P

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Junta de Andalucía TIC-6091

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