MRAPI Resource Management Layer on Reconfigurable Systems-on-Chip
- Others:
- Embedded System Lab (ESL) ; Thales Research and Technology
- Equipes Traitement de l'Information et Systèmes (ETIS - UMR 8051) ; Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY)
- Laboratoire d'Electronique, Antennes et Télécommunications (LEAT) ; Université Nice Sophia Antipolis (1965 - 2019) (UNS) ; COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-Centre National de la Recherche Scientifique (CNRS)-Université Côte d'Azur (UCA)
Description
A major challenge of heterogeneous reconfigurable System-on-Chip (SoC) is how to fulfil inter-processing element communication without sacrificing performance, ease of programming and portability. In such a platform, the application is divided into threads managed by an operating system, and whereas some threads are implemented as hardware accelerators that can run across different partitions of the chip, others run as software threads on embedded processors. Relying on the Multicore Resource management API (MRAPI) specification and client-server mechanisms, this article describes a way to provide hardware threads the same kind of access to OS services that software threads have, whatever is the core they are running on. As a case-study, we introduce in this work a real implementation (SW and HW) of this API and quantifies the overhead cost of this abstraction layer on top of an operating system.
Abstract
International audience
Additional details
- URL
- https://hal.science/hal-00987324
- URN
- urn:oai:HAL:hal-00987324v1
- Origin repository
- UNICA