Published October 3, 2017
| Version v1
Publication
Fault Attack on FPGA implementations of Trivium Stream Cipher
Description
This article presents the development of an experimental
system to introduce faults in Trivium stream ciphers
implemented on FPGA. The developed system has made possible
to analyze the vulnerability of these implementations against
fault attacks. The developed system consists of a mechanism
that injects small pulses in the clock signal, and elements that
analyze if a fault has been introduced, the number of faults
introduced and its position in the inner state. The results obtained
demonstrate the vulnerability of these implementations against
fault attacks. As far as we know, this is the first time that
experimental results of fault attack over Trivium are presented.
Abstract
Ministerio de Economía y Competitividad TEC2010-16870Abstract
Ministerio de Economía y Competitividad TEC2013-45523- RAbstract
Ministerio de Economía y Competitividad CSIC 201550E039)Additional details
Identifiers
- URL
- https://idus.us.es/handle/11441/64960
- URN
- urn:oai:idus.us.es:11441/64960