LVDS interface for AER links with burst mode operation capability

Description

This paper presents the design and simulation of a serial AER LVDS communication link. It converts data from classical AER parallel bus with a 4-phase handshaking protocol into a bit stream which is transmitted serially into a single LVDS wire. At the receiver side data from the LVDS cable are transformed back to a parallel AER bus and handshaking signals are also properly managed. The link has been designed in a 90 nms technology. Extensive simulations have been performed demonstrating that the link can operate at a speed of 1 Gbps for all the technology corners, exhibiting a power consumption of 27.8 mW for the transmitter and 12.3 mW for the receiver. In the simulation the transmission channel was modelled as a 50 cm cat5E UTP cable, connected to the AER chip through 5 cm PCB traces modelled as a coupled microstrip transmission line. The design has been completed up to the layout level and has been submitted for fabrication. The transmitter and the receiver take up an area of 311x148 μm2 and 300x148 μm2 respectively.

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European Union IST-2001-34124 (CAVIAR)

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Ministerio de Educación y Ciencia TIC-2003-08164-C03- 01

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Ministerio de Educación y Ciencia TEC2006-11730-C03-01

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Junta de Andalucía P06-TIC-01417

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