Low-power differential logic gates for dpa resistant circuits

Description

Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is a SCA that uses the power consumption dependence on the processed data. Designers widely use differential logic styles with constant power consumption to protect devices against DPA. However, the right use of such circuits needs a fully symmetric structure and layout, and to remove any memory effect that could leak information. In this paper we propose improved low-power gates that provide excellent results against DPA attacks. Simulationbased DPA attacks on Sbox9 are used to validate the effectiveness of the proposals.

Abstract

España TEC2010-16870 IPT2012-0695-390000 TEC2013-45523-R

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