A 6.3 pJ/b Ultra-low Power Energy Detector for Non-Coherent UWB Impulse Radio Receiver

Description

This paper presents a 130nm CMOS (HCMOS9 from ST-Microelectronics) 6.3 pJ/b ultra-low power energy detector circuit design and implementation. The designed energy detector is implemented with three blocks: the squarer based on a MOS transistor biased in the subthreshold region, the integrator based on a low pass amplifier and a decision circuit. The energy detector is driven by a LNA of 30 dB gain. The experimental results show that a BER of 10 –3 is achieved for a peak to peak voltage of 3.4 mV at receiver input for a data rate of 100 Mb/s, leading to a receiver sensitivity of -58.4 dBm. The energy power consumption is 0.63 mW resulting in an energy of 6.3 pJ/b. The overall Rx power consumption is 14.4 mW (100 % duty cycled) with a 1.2 V supply voltage when the receiver is always on. This value is drastically reduced with a power gating technique due to the duty cycle of the IR-UWB pulses. For example, assuming an on-stage window of 5 ns, the total power consumption becomes 7.2 mW @ 100 Mb/s. The chip area is 1.43 mm 2 .

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