Published January 9, 2024
| Version v1
Publication
Efficient realisation of MOS-NDR threshold logic gates
Description
A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.
Abstract
Gobierno de España - NDR, TEC2007-67245/MIC
Abstract
Junta de Andalucía - Proyecto de Excelencia TIC-2961
Additional details
- URL
- https://idus.us.es/handle//11441/153087
- URN
- urn:oai:idus.us.es:11441/153087
- Origin repository
- USE