Delay and power consumption of static bulk-CMOS gates using independent bodies

Description

Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages obtained can justify its utilization in selected parts of the circuits. This is discussed in this paper.

Abstract

Ministerio de Educación y Ciencia TEC2007-61802/MIC (HIPER)

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