Published July 23, 2018
| Version v1
Publication
Inertial and Degradation Delay Model for CMOS Logic Gates
Description
The authors present the Inertial and Degradation
Delay Model (IDDM) for CMOS digital simulation. The
model combines the Degradation Delay Model presented in
previous papers with a new algorithm to handle the inertial effect,
and is able to take account of the propagation and filtering
of arbitrarily narrow pulses (glitches, etc.). The model clearly
overcomes the limitations of conventional approaches.
Additional details
Identifiers
- URL
- https://idus.us.es/handle//11441/77511
- URN
- urn:oai:idus.us.es:11441/77511
Origin repository
- Origin repository
- USE