A low-voltage /spl radic/x floating-gate MOS integrator

In this paper, the design and simulation results of an IV integrator using floating gate MOS (FGMOS) transistor techniques is presented. Combining FGMOS working in strong and in weak inversion a current-mode companding integrator is proposed implemented in a standard CMOS process is able to work with very low supply voltage. It has application in audio signal processing. Simulation results show a very low power consumption (1.3 /spl mu/W), low frequencies below 5 Hz feasible, and a dynamic range of 55 dB for a maximum THD=1.2%. The gain of the integrator is adjustable in more than 2 decades.