Fast Hardware Implementations of Static P Systems

Description

In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.

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Ministry of Science and Innovation of the Spanish Government under the project TEC2011-27936 (HIPERSYS)

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European Regional Development Fund (ERDF)

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Ministry of Education of Spain (FPU grant AP2009-3625)

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ANR project SynBioTIC

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