Hierarchical modeling of a fractional phase locked loop

Description

The aim of this study is to provide a multi level VHDL-AMS model-ing of an analog Phase Locked Loop (PLL). Three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. The characteristic parameters of the PLL, such as the settling time, overshoot, volt-age variations linked to charge pump architecture and final voltage are extracted from the intermediate level.

Abstract

International audience

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