Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18

Efficient acceleration of deep convolutional neural networks is currently a major focus in Edge Computing research. This paper presents a realistic case study on ResNet-18, exploring Partial Reconfiguration (PR) as an alternative to the standard static reconfigurable approach. The PR strategy is based on sequencing the layers of the DNN on a single reconfigurable region to significantly reduce the amount of Programmable Logic (PL) resources required. Results demonstrate that PRbased acceleration can reduce FPGA resource usage by over 6 times, power consumption by 3.2 times, and the corresponding global energy cost by 2.7 times, with only a 17.5% increase in execution time. This approach shows great potential for further reductions in area and power consumption.