Four-quadrant one-transistor-synapse for high-density CNN implementations

Description

Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.

Abstract

Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-02

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