Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs

Description

This work presents a unified framework to design, implement and evaluate the performance of Ring Oscillator Physical Unclonable Functions (RO PUFs) on FPGAs. The design flow uses a Digital Signal Processing (DSP) tool integrated into the Matlab environment. The use of this tool eases the evaluation of the PUF performance. The DSP tool provides an environment to apply the challenges to the RO PUF, acquire the responses by using hardware (HW) co-simulation, and compute a set of metrics to quantify the stability, probability and entropy of the PUF response. Additionally, the robustness of the PUF response is proved in the generation of secret keys. The design flow was applied to evaluate the performance of RO PUFs implemented on 17 Basys 3 Artix-7 FPGA Boards.

Abstract

Programa Horizon 2020 de la Unión Europea-SPIRS 952622

Abstract

Ministerio de Ciencia e Innovación y Agencia Estatal de Investigación de España MCIN/AEI-PID2020-116664RBI00 y MCIN/AEI/10.13039/501100011033

Abstract

Consejo Superior de Investigaciones Científicas (CSIC)-LINKA20216

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