Clock Management and Analysis for Transaction-Level Virtual Prototypes

Description

Designing power efficient systems requires both the right low power SoC architecture and the appropriate power management software. Designer/developer teams need to address this requirement as early as possible in the development cycle. Electronic System Level (ESL) tools and methods for virtual prototyping are available nowadays to help developers in that task. This work introduces how clock management for reducing dynamic power consumption in a virtual prototype can be investigated at Transaction-Level by inserting abstract models of a clock intent and of power management capabilities. Using Synopsys Platform Architect MCO [1], our approach has been validated with an audio virtual platform. Results show the benefits of modeling the real power management strategy such that expected performance and power budget are achieved while verifying coherency between functional model and power inte

Abstract

International audience

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