Using Model Driven Engineering to Reliably Accelerate Early Low Power Intent Exploration for a System-on-Chip Design

Defining low power design intent for a system-on-chip (SoC) consists in specifying its power management architecture and strategy according to specific low power techniques such as power gating and multi-voltage scaling requirements. Choosing the most-energy efficient power intent for a final system contributes widely to reduce its overall power consumption. At Transaction-Level, a rapid exploration of different power intent alternatives can be made. In this paper*, we present a Model Driven Engineering (MDE) approach to automate low power design intent specifications and accelerate Low Power Design Intent Space Exploration (LPDISE) using a Transaction-Level power-aware design methodology. This MDE approach mainly relies on a high level abstraction of the Unified Power Format (UPF) standard concepts that fit a TLM approach use. Then, the MDE approach is applied to automatically generate a UPF code defining the most energy-efficient power intent and being a reference file for Register Transfer Level (RTL) design team. This task focuses on a smart deduction of adequate UPF commands from the high level abstraction semantics. The effectiveness of the proposed MDE approach is illustrated by an example.