Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies

In the field of logic simulation, the constant advance of technology influences remarkably in the circuits dynamic behavior. Our main aim is to increase precision of logic simulators by taking into account this influence. This task has two main objectives: (a) developing a model for logic gates that unifies the functional behavior and the dynamic one and (b) developing techniques that improve the characterization processes by using accurate and feasible characterization methods to reduce the error introduced during parameters extraction. The first task has yielded to develop the Internode model, what is based on a finite state machine that represents the internal state of the gate depending on the electrical local of its internal nodes. Such model allows simulators to take into account all the power consumption cases (not only the usually considered ones). On the second task, we have developed a characterization technique based on the use of sampled signals. This technique has improved measurement precision by 5%-8% in the SCMOS inverter case (350 nm technology).