Published June 3, 2007 | Version v1

Conference paper Metadata-only

Top-Down PLL Design Methodology Combining Block Diagram, Behavioral, and Transistor-Level Simulators

Contributors

Other:

Laboratoire d'Electronique, Antennes et Télécommunications (LEAT) ; Université Nice Sophia Antipolis (1965 - 2019) (UNS) ; COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-Centre National de la Recherche Scientifique (CNRS)

International audience

Additional details

URL: https://hal.science/hal-00160824
URN: urn:oai:HAL:hal-00160824v1

Origin repository: UNICA

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Created: February 28, 2023
Modified: April 7, 2025