Published July 8, 2024
| Version v1
Publication
Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
Contributors
Others:
- Universidad de Sevilla. Departamento de Tecnología Electrónica
- Universidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtos
- Universidad de Sevilla
- Junta de Andalucía
- European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)
- European Union (UE). H2020
- Ministerio de Ciencia e Innovación (MICIN). España
Description
In this paper, we present a review of the work [1].
The fast settlement of Privacy and Secure operations in the
Internet of Things (IoT) is appealing the selection of mechanisms
to achieve a higher level of security at the minimum cost and with
reasonable performances. In recent years, dozens of proposals
have been presented to design circuits resistant to Power Analysis
attacks. In this paper a deep review of the state of the art of
gate-level countermeasures against Power Analysis attacks has
been done, performing a comparison between hiding approaches
(the power consumption is intended to be the same for all the
data processed) and the ones considering a masking procedure
(the data are masked and behave as random). The most relevant
proposals in the literature, 35 for hiding and 6 for masking, have
been analyzed, not only by using data provided by proposers,
but also those included in other references for comparison.
Additional details
Identifiers
- URL
- https://idus.us.es/handle//11441/161172
- URN
- urn:oai:idus.us.es:11441/161172
Origin repository
- Origin repository
- USE