An ESL framework for low power architecture design space exploration

Description

Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows at transactional level are missing. In this paper we describe how a power/clock intent could be described at transactional level using a separation of concerns process and how the transactional simulation code merging functional and power behaviors can be generated automatically using a model-driven engineering approach.

Abstract

International audience

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