Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera

Description

This paper describes a methodology to improve the energy efficiency of high-performance mul-tiprocessor architectures with Dynamic and Partial Reconfiguration (DPR), based on a thorough application study in the field of smart camera technology. FPGAs are increasingly being used in cameras owing to their suitability for real-time image processing with intensive, high-performance tasks, and to the recent advances in dynamic reconfiguration that further improve energy efficiency. The approach used to best exploit DPR is based on the better coupling of two decisive elements in the problem of heterogeneous deployment: design space exploration and advanced scheduling. We show how a tight integration of exploration, energy-aware scheduling , common power models, and decision support in heterogeneous DPR multiprocessor SoC mapping can be used to improve the energy efficiency of hardware acceleration. Applying this to a mobile vehicle license plate tracking and recognition service results in up to a 19-fold improvement in energy efficiency compared with software multiprocessor execution (in terms of energy–delay product), and up to more than a 3-fold improvement compared with a multipro-cessor with static hardware acceleration (i.e. without DPR).

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