DUHEM , François

Despite promising capabilities, FPGAs partial reconfiguration feature is not anchored in the industry yet, mostly for two reasons. First of all, Xilinx controller shows low performance and might introduce a large time overhead compared to the task period, incompatible with the use of partial reconfiguration. Also, developing such a dynamic...

A simulator for hardware Spiking Neural Networks have been developed, in order to evaluate different implementation architectures in terms of processing latency, energy consumption, and chip surface. This simulator integrates different types of architectures, memory units distribution and memory technologies, in order to find which...

In this paper, we present a flow enabling design space exploration for partially reconfigurable systems with real-time constraints, called FoRTReSS. FoRTReSS allows estimating mixed hardware/software implementations of an application where the hardware design space, the floorplanning of reconfigurable regions placed on the FPGA, is...

This paper describes a methodology to improve the energy efficiency of high-performance mul-tiprocessor architectures with Dynamic and Partial Reconfiguration (DPR), based on a thorough application study in the field of smart camera technology. FPGAs are increasingly being used in cameras owing to their suitability for real-time image...