MORGADO GARCÍA DE LA POLAVIEJA , Alonso

This work presents two novel topologies of cascade ΣΔ modulators with unity signal transfer function that avoid the need of digital filtering in the error cancellation logic. The combination of these two aspects make them highly tolerant to noise leakages, very robust to non-linearit ies of the ...

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cascades while presenting very relaxed output swing requirements and, subsequently, high robustness to non-linearities of the amplifiers. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the...

A new cascade ΣΔ modulator architecture with unity signal transfer function is presented, which avoids the need for digital filtering in the error cancellation logic. The combination of these two aspects makes it highly tolerant to noise leakages, very robust to nonlinearities of the circuitry and especially suited for low-voltage...

This paper presents the design and implementation of a fourth-order band-pass continuous-time modulator intended for the digitization of radio-frequency signals in softwaredefined- radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in...

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multistandard wireless terminals, covering three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuitlevel in order to adapt its performance to the different standard specifications with optimized power consumption. The design...

This paper presents innovative architectures of hybrid Continuous-Time/Discrete-Time (CT/DT) cascade ΣΔ Modulators (ΣΔMs) made up of a front-end CT stage and a back-end DT stage. In addition to increasing the digitized signal bandwidth as compared to conventional ΣΔMs, the proposed topologies take advantage of the CT nature of the front-end ΣΔM...

This paper presents a new adaptable cascade ΣΔ modulator architecture fo r low-voltage multi-stan- dard applications. It uses two reconfiguration strategies: a programmable global resonation and a variable loop-filter order. These techniques are properly com- bined in a novel topology that allows to increase the effec- tive resolution in a...

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and...

This paper presents two new architectures of cascade ΣΔ modulators that, based on the use of resonation, allow to increase the effective resolution compared to previously reported topologies whereas keeping relaxed output swing and high robustness to non-linearities of the amplifiers. In addition, the use of loop filters based on Forward-Euler...

This paper presents a new two-stage cascade ΣΔ modula- tor architecture that uses inter-stage resonation to increase its effec- tive resolution as compared to conventional cascades and avoids the need for digital filtering in the error cancellation logic. The combi- nation of these two strategies, together with the use of unity signal transfer...

This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration...

This paper presents design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multi-standard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration...