AFFES , Hend

Embedded systems-on-chip (SoC) invade our daily life. With advances in semiconductor technology, these systems integrate more and more complex and energy-intensive features which generate increasing computation load and memory size requirements. While the complexity of these systems is a key trend, energy consumption has emerged as a critical...

Dynamic power management (DPM) has become a major technique for reducing power consumption in SoCs. One of the main challenges in DPM is to predict as soon as a component enters in idle mode if it will stay in this mode for a time longer than a minimum value that leads to power savings. Even if a component in power off state does not consume...

International audience

The paper1 describes a dynamic power management (DPM) strategy independent from application and operating system layers, but easily controllable by these layers. Challenges in defining an efficient power management policy include a relevant prediction mechanism of idle period of hardware components and the ability to wake-up components in sleep...

In most applications, power consumption has become a major criterion in the design of embedded electronic devices. The requirements of target applications may influence the design of systems with very low power consumption or with managed temperature, or a combination of the two for some systems. Mobile and embedded systems powered by batteries...

Due to the ever-increasing demands on energy efficiency, designers are struggling to construct efficient and correct power management strategies for complex System-on- Chips (SoCs). The validation of an efficient power intent for a SoC is challenging and should be considered at early stage of the electronic system-level (ESL) design flow. To...

National audience

Déclaration d'Invention déposée auprès de la Délégation Régionale Côte d'Azur CNRS.Cette librairie de modèles permet de structurer un modèle fonctionnel d'une architecture modélisée en SystemC-TLM pour décrire le partitionnement de ses composants fonctionnels en domaines de puissance (power domains) et en domaines d'horloge (clock domains),...

Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design...

National audience

Designing power efficient systems requires both the right low power SoC architecture and the appropriate power management software. Designer/developer teams need to address this requirement as early as possible in the development cycle. Electronic System Level (ESL) tools and methods for virtual prototyping are ...

International audience