BONAMY , Robin

There has been a lot of research to support the benefits of reconfigurable hardware acceleration in high performance low power System-on-Chips. Despite numerous advances made over the last two decades, especially in code generation support, reconfigurable system-on-chips still face application programming challenges. As the full automated...

This paper describes an energy-aware scheduling approach intended for use in heterogeneous multiprocessors supporting hardware acceleration with Dynamic and Partial Re-configuration. Scheduler decisions rely on pragmatic power and energy models to map the load across cores and reconfigurable regions with regards to the actual power costs....

Minimizing the energy consumption and silicon area are usually two major challenges in the design of battery-powered embedded computing systems. Dynamic and Partial Reconfiguration (DPR) opens up promising prospects with the ability to reduce jointly performance and area of compute-intensive functions. However, partial reconfiguration...

National audience

Nowadays, System-on-Chip architectures are composed of several execution resources which support complex applications. As it shares silicon area and limits the cost of the global circuit, the embedding of a reconfigurable resource in these SoC provides flexibility to the hardware. In this case, several implementations of the same algorithm,...

International audience

Although fairly known for a long time, the vast potential of Dynamic and Partial Reconfigu-ration (DPR) for high energy efficiency is still difficult to exploit, for reasons that are more methodological than purely technical. This work addresses this problem and provides a contri-bution by seeking to improve energy efficient deployment and...

This paper exhaustively explores the potential energy efficiency improvements of Dynamic and Partial Reconfiguration (DPR) on the concrete implementation of a H.264/AVC video decoder. The methodology used to explore the different implementations is presented and formalized. This formalization is based on pragmatic power consumption models of...

In the context of embedded systems development, two important challenges are the efficient use of silicon area and the energy consumption minimization. Hardware accelerated tasks allow to reduce energy consumption of several orders of magnitude, compared to software execution, but these tasks require silicon area and consume power even when...

In this paper, we present a flow enabling design space exploration for partially reconfigurable systems with real-time constraints, called FoRTReSS. FoRTReSS allows estimating mixed hardware/software implementations of an application where the hardware design space, the floorplanning of reconfigurable regions placed on the FPGA, is...

International audience

International audience

This paper describes a methodology to improve the energy efficiency of high-performance mul-tiprocessor architectures with Dynamic and Partial Reconfiguration (DPR), based on a thorough application study in the field of smart camera technology. FPGAs are increasingly being used in cameras owing to their suitability for real-time image...