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April 16, 2015 (v1)PublicationUploaded on: March 27, 2023
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March 10, 2020 (v1)Publication
This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of an array of 32×32 completely programmable CNN cells. Input image can be loaded in optical or electrical form. Accuracy is in the range of 7-8 bit, and cell density is of 33 cells/mm2.
Uploaded on: March 27, 2023 -
February 24, 2020 (v1)Publication
Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision system is due to the inherent parallelism of the former. In particular, the retina combines image sensing and parallel processing to reduce the amount of data transmitted for subsequent processing by the following stages of...
Uploaded on: December 5, 2022 -
March 9, 2020 (v1)Publication
This paper describes the design of a programmable Cellular Neural Network (CNN) chip, with additional functionalities similar to those of the CNN Universal Chip. The prototype, which contains 1024 cells, has been designed in a 1.0μm, n-well CMOS technology. A careful selection of the topology and design parameters has resulted in a cell density...
Uploaded on: March 27, 2023 -
November 5, 2019 (v1)Publication
Explores the design of cellular neural networks (CNN) by using sampled-data analog current-mode techniques which neither requires capacitors nor resistors but just MOS transistors. The feature makes the proposed technique well suited for implementation in conventional VLSI MOS technologies. A set of building blocks is presented and their...
Uploaded on: March 27, 2023 -
March 31, 2020 (v1)Publication
The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5pA) and high-speed for low input currents (8ns at 50nA). The new structure features a speed improvement of more than two orders of magnitude for a 1 nA input current, when compared to the fastest reported to date.
Uploaded on: December 4, 2022 -
November 8, 2019 (v1)Publication
This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current...
Uploaded on: December 5, 2022 -
October 21, 2019 (v1)Publication
This paper explores different trade-offs associated with the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing the power consumption, increasing the operation speed, and reducing the area occupation (i.e., increasing the density of...
Uploaded on: December 4, 2022 -
February 24, 2020 (v1)Publication
Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area...
Uploaded on: December 5, 2022 -
March 20, 2020 (v1)Publication
A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind of problem in MOS VLSI. This architecture is a fully programmable and reconfigurable one exploiting SC techniques for the...
Uploaded on: December 4, 2022 -
October 31, 2019 (v1)Publication
A systematic approach for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques is presented. The method is based on formulating a dynamic gradient system whose state evolves in time towards the solution point of the corresponding programming problem. A neuron cell for the linear...
Uploaded on: December 4, 2022 -
October 4, 2019 (v1)Publication
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory (cache) on a common silicon substrate. This chip, designed in a 0.5 /spl mu/m CMOS standard technology contains around 1000000 transistors, 80% of which operate...
Uploaded on: March 25, 2023 -
January 30, 2020 (v1)Publication
The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 × 3 convolution masks. The vision chip has been...
Uploaded on: March 27, 2023 -
March 31, 2020 (v1)Publication
A circuit for online solving of linear programming problems is presented. The circuit uses switched-capacitor techniques and is thus suitable for monolithic implementation. The connection of the proposed circuit to analogue neural networks is also outlined.
Uploaded on: March 27, 2023 -
March 10, 2020 (v1)Publication
Stability and convergency results are reported for a modified continuous-time CNN model. The signal range of the state variables is equal to the unitary interval, independently of the application. Stability and convergency properties are similar to those of the original model and, for given templates and offset coefficients, the results are...
Uploaded on: December 4, 2022 -
February 25, 2020 (v1)Publication
This paper describes a hybrid weight-control strategy for VLSI realizations of programmable Cellular Neural Networks (CNNs), based on auto-tuning of analog control signals to digitally specified values. The approach merges the advantages of digital and analog programmability, achieving low areas and reduced number of control lines, simplifying...
Uploaded on: December 4, 2022 -
October 3, 2018 (v1)Publication
This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabrication in a 0.35μm standard digital 1P-5M CMOS Technology. The chip has been designed to achieve the high-speed and moderate-accuracy constraints of most real time image...
Uploaded on: March 27, 2023 -
March 25, 2020 (v1)Publication
A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range centring according to illumination conditions are presented. The high output current levels allow the use of these devices in continuoustime asynchronous imagers, as well as in high-sampling-frequency applications.
Uploaded on: March 27, 2023 -
April 20, 2020 (v1)Publication
This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in...
Uploaded on: March 27, 2023 -
March 10, 2020 (v1)Publication
This paper describes a hybrid weight-control strategy for the VLSI realization of programmable CNNs, based on automatic adaptation of analog control signals to levels specified by digital words. This approach merges the advantages of digital and analog programmability, achieving low areas and reduced number of control lines, simplifying the...
Uploaded on: December 5, 2022 -
November 19, 2018 (v1)Publication
This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component Detection (CCDet) [2]. Projection direction can be selected among four different possibilities. Every cell (or pixel) in the 32 x 32 array includes a photosensor circuitry and an automatic tuning circuitry to adapt to average...
Uploaded on: December 4, 2022 -
October 25, 2019 (v1)Publication
An operational vision-chip prototype with a wide-range of potential applications in artificial-vision systems is presented. Its functionality includes concurrent image-transduction, programmable image-processing, image-storage, and algorithmic control over a network of 20/spl times/22 identical cells. The prototype has been designed and...
Uploaded on: March 27, 2023