Las aportaciones principales de esta Tesis se refieren al diseño de circuitos electrónicos con las primitivas disponibles en tecnologías CMOS standard, y a la integración monolítica de los mismos en chips de altas y muy-altas densidad de integración. Cuando nos referimos al diseño de circuitos electrónicos es usual marcar una frontera entre...
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February 26, 2018 (v1)PublicationUploaded on: March 27, 2023
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March 10, 2020 (v1)Publication
This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of an array of 32×32 completely programmable CNN cells. Input image can be loaded in optical or electrical form. Accuracy is in the range of 7-8 bit, and cell density is of 33 cells/mm2.
Uploaded on: March 27, 2023 -
February 24, 2020 (v1)Publication
Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision system is due to the inherent parallelism of the former. In particular, the retina combines image sensing and parallel processing to reduce the amount of data transmitted for subsequent processing by the following stages of...
Uploaded on: December 5, 2022 -
March 9, 2020 (v1)Publication
This paper describes the design of a programmable Cellular Neural Network (CNN) chip, with additional functionalities similar to those of the CNN Universal Chip. The prototype, which contains 1024 cells, has been designed in a 1.0μm, n-well CMOS technology. A careful selection of the topology and design parameters has resulted in a cell density...
Uploaded on: March 27, 2023 -
October 21, 2019 (v1)Publication
This paper explores different trade-offs associated with the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing the power consumption, increasing the operation speed, and reducing the area occupation (i.e., increasing the density of...
Uploaded on: December 4, 2022 -
February 24, 2020 (v1)Publication
Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area...
Uploaded on: December 5, 2022 -
October 4, 2019 (v1)Publication
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory (cache) on a common silicon substrate. This chip, designed in a 0.5 /spl mu/m CMOS standard technology contains around 1000000 transistors, 80% of which operate...
Uploaded on: March 25, 2023 -
January 30, 2020 (v1)Publication
The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 × 3 convolution masks. The vision chip has been...
Uploaded on: March 27, 2023 -
March 10, 2020 (v1)Publication
Stability and convergency results are reported for a modified continuous-time CNN model. The signal range of the state variables is equal to the unitary interval, independently of the application. Stability and convergency properties are similar to those of the original model and, for given templates and offset coefficients, the results are...
Uploaded on: December 4, 2022 -
February 25, 2020 (v1)Publication
This paper describes a hybrid weight-control strategy for VLSI realizations of programmable Cellular Neural Networks (CNNs), based on auto-tuning of analog control signals to digitally specified values. The approach merges the advantages of digital and analog programmability, achieving low areas and reduced number of control lines, simplifying...
Uploaded on: December 4, 2022 -
October 3, 2018 (v1)Publication
This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabrication in a 0.35μm standard digital 1P-5M CMOS Technology. The chip has been designed to achieve the high-speed and moderate-accuracy constraints of most real time image...
Uploaded on: March 27, 2023 -
March 25, 2020 (v1)Publication
A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range centring according to illumination conditions are presented. The high output current levels allow the use of these devices in continuoustime asynchronous imagers, as well as in high-sampling-frequency applications.
Uploaded on: March 27, 2023 -
April 20, 2020 (v1)Publication
This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in...
Uploaded on: March 27, 2023 -
March 10, 2020 (v1)Publication
This paper describes a hybrid weight-control strategy for the VLSI realization of programmable CNNs, based on automatic adaptation of analog control signals to levels specified by digital words. This approach merges the advantages of digital and analog programmability, achieving low areas and reduced number of control lines, simplifying the...
Uploaded on: December 5, 2022 -
November 19, 2018 (v1)Publication
This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component Detection (CCDet) [2]. Projection direction can be selected among four different possibilities. Every cell (or pixel) in the 32 x 32 array includes a photosensor circuitry and an automatic tuning circuitry to adapt to average...
Uploaded on: December 4, 2022 -
October 25, 2019 (v1)Publication
An operational vision-chip prototype with a wide-range of potential applications in artificial-vision systems is presented. Its functionality includes concurrent image-transduction, programmable image-processing, image-storage, and algorithmic control over a network of 20/spl times/22 identical cells. The prototype has been designed and...
Uploaded on: March 27, 2023 -
January 31, 2020 (v1)Publication
This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The chip has been designed to achieve the high-speed and moderate-accuracy (8b) requirements of most real time early-vision...
Uploaded on: March 27, 2023 -
January 28, 2020 (v1)Publication
From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (∼...
Uploaded on: December 4, 2022 -
April 13, 2020 (v1)Publication
This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated...
Uploaded on: December 4, 2022 -
March 12, 2020 (v1)Publication
An architecture and related building blocks are presented for the realization of image processing tasks using current-mode analog-digital circuits. The architecture is based on the Cellular Neural Network paradigm while implementation is made using switched-current circuit techniques. Since just MOS transistors are required as circuit...
Uploaded on: March 27, 2023 -
April 1, 2020 (v1)Publication
A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order piecewise-finear discrete map which yields a hopping transition between regions of chaotic motions and hence produces 1 / fYnoise. Experimental results from a parasitics-insensitive prototype are included demonstrating...
Uploaded on: March 27, 2023 -
March 17, 2020 (v1)Publication
An analog-digital system is presented for the generation of truly random (aperiodic) digital sequences. This model is based on a very simple piecewise-linear discrete map which is suitable for implementation using monolithic analog sampled-data techniques. Simulation results are given illustrating the optimum choice of the model parameters....
Uploaded on: March 27, 2023 -
March 25, 2020 (v1)Publication
A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the implementation of a very simple chaotic discrete-time system. The concept is demonstrated via a 3ftm CMOS double-metal double-poly monolithic prototype yielding a 4V peak-to- peak signal with a flat power density spectrum from DC...
Uploaded on: December 4, 2022 -
February 24, 2020 (v1)Publication
This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new prototype, called CNNUC3, follows the cellular neural network universal machine computing paradigm. Due to its very advanced features and algorithmic capabilities, this chip has been demonstrated to be able to perform not...
Uploaded on: March 27, 2023