N
B
Last name: NICOLLE
First name: B.
Master STIC Recherche, option Télécommunications RF et Micro-électronique
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The aim of this study is to provide a multi level VHDL-AMS model-ing of an analog Phase Locked Loop (PLL). Three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. The characteristic parameters of the PLL, such as the settling time, overshoot, volt-age variations linked to charge pump...
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This papers shows a way of using the ADVance MS environment to simulate a low noise amplifier (LNA) and compare these simulations with high (behavioral and block) level models. This work is the first step in the development of a global system modeling and simulation platform For the LNA study, we chose a top-down approach although a bottom-up...
The aim of this study is to provide a multi level VHDL-AMS model-ing of an analog Phase Locked Loop (PLL). Three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. The characteristic parameters of the PLL, such as the settling time, overshoot, volt-age variations linked to charge pump...
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The aim of this study is to provide a high-level VHDL-AMS model for multi-standard phase locked loop in SOI technology. The supported standards are GSM, GPS, DCS, Bluetooth, Wifi and WLAN. The model can be used to evaluate settling times, channel-to-channel transition times and also the timing needed to switch from one standard to another one....
The aim of this study is to provide a high-level VHDL-AMS model for multi-standard phase locked loop in SOI technology. The supported standards are GSM, GPS, DCS, Bluetooth, Wifi and WLAN. The model can be used to evaluate settling times, channel-to-channel transition times and also the timing needed to switch from one standard to another one....
In order to generate a first-time right design, system level modeling and simulation is a major step. Thus, performance evaluation of integrated wireless systems requires the development of RF behavioral models compatible with the microelectronic design tools. Firstly, this paper shows the need of such models within the RFIC Top–Down design...
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This paper deals with the design of a fractional PLL for wireless multi-standard applications. This circuit has been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. Five standards are covered by this structure: GSM (900 MHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11a (5.8...
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