This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current...
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May 8, 2018 (v1)PublicationUploaded on: March 27, 2023
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May 21, 2018 (v1)Publication
In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions...
Uploaded on: March 27, 2023 -
July 4, 2018 (v1)Publication
In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given...
Uploaded on: March 27, 2023 -
February 20, 2018 (v1)Publication
This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The method is based on a nonnecessarily polynomial continuous and differentiable mathematical model of the converter transfer function, and on the spectral processing of the converter output under a sinusoidal input excitation....
Uploaded on: March 27, 2023 -
September 20, 2017 (v1)Publication
This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and...
Uploaded on: December 4, 2022 -
July 20, 2018 (v1)Publication
This paper presents a semi-empirical modeling of MOST and passive elements to be used in narrowband radiofrequency blocks for nanometer technologies. This model is based on a small set of look-up tables (LUTs) obtained via electrical simulations. The MOST description is valid for all-inversion regions of MOST and the data is extracted as...
Uploaded on: March 27, 2023 -
September 19, 2018 (v1)Publication
Σ∆ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency range. As a result Σ∆ modulators are often the preferred option for sensor and instrumentation. Offset and Flicker noise are usual concerns for this type of applications and one way to...
Uploaded on: March 27, 2023 -
March 23, 2018 (v1)Publication
Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize...
Uploaded on: December 5, 2022 -
July 10, 2018 (v1)Publication
Using several ADCs (Analog to Digital Converters) in parallel with convenient time offsets is considered as an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this time-interleaving technique is that any mismatch between the channels will damage the precision. This paper gives a probabilistic...
Uploaded on: December 4, 2022 -
May 10, 2018 (v1)Publication
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference....
Uploaded on: March 27, 2023 -
April 30, 2018 (v1)Publication
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design methodology are: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design...
Uploaded on: December 4, 2022 -
June 18, 2018 (v1)Publication
A formal set of design decisions can aid in using oscillation-based test (OBT) for analog subsystems in SoCs. The goal is to offer designers testing options that do not have significant area overhead, performance degradation, or test time. This work shows that OBT is a potential candidate for IP providers to use in combination with functional...
Uploaded on: December 4, 2022 -
July 10, 2018 (v1)Publication
This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results...
Uploaded on: December 5, 2022 -
February 29, 2024 (v1)Publication
Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently avail- able, and can potentially be used to emulate the functioning of neurons in computational neuromor- phic systems. As they oscillate in the 4–20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due...
Uploaded on: March 3, 2024 -
June 4, 2018 (v1)Publication
This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The filter compliants with the requirements of the IEEE802.15.4 standard. Simulation results including mismatching and process...
Uploaded on: December 5, 2022