VALENCIA BARRERO , Manuel

En la última década hemos asistido a la penetración de los sistemas digitales en la vida cotidiana. Por citar sólo un ejemplo, señalemos que los computadores digitales se han convertido en herramienta básica del trabajo científico, administrativo, industrial, militar y educacional. Incluso áreas que tradicionalmente no han estado incluidas...

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Modular multiplication is the key operation in systems based on public key encryption, both for RSA and elliptic curve (ECC) systems. High performance hardware implementations of RSA and ECC systems use the Montgomery algorithm for modular multiplication, since it allows results to be obtained without performing the division operation. The aim...

Ministerio de Economía y Competitividad TEC2013-45523-R

This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The de-sign was simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. The aim of this paper is to evaluate the suitability of...

This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and...

En esta comunicación se presenta la realización de una actividad teórico-práctica, encuadrada dentro del marco ECTS, para un primer curso de Electrónica Digital. Está ideada para desarrollarse en un entorno de bajo coste y de forma que el alumno tenga a su disposición ayudas a diferentes niveles (información jerarquizada). Partiendo de un...

This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project....

Se describe una familia de redes de interconexión para sistemas multiprocesadores. Estas redes utilizan buses múltiples estructurados en varios niveles e incorporan el concepto de tolerancia a fallos mediante redundancia en las vías de comunicación. Sus principales características son: buena relación coste/ rendimiento, fiabilidad, modularidad...

A practical N-user arbiter and its implementation are presented in this correspondence. Because of the asynchronous character of its input variables (request signals), the design proposed is asynchronous and keeps in mind the possibility of metastable operations. The structure of the arbiter is very simple and modular.

The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to reduce the power consumption as well as the switching noise generation. A measurement methodology to establish right comparisons between different implementations of gateclocked counters is presented. Basically two ways of...

The security of cryptocircuits is today threatened not only by attacks on algorithms but also, and above all, by attacks on the circuit implementations themselves. These are known as side channel attacks. One variety is the Active Fault Analysis attack, that can make a circuit vulnerable by changing its behavior in a certain way. This article...

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