Encadré par Miichel Auguin
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September 2014 (v1)ReportUploaded on: December 4, 2022
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September 15, 2014 (v1)Report
Encadré par M.Michel AUGUIN,Mme. Hend AFFES
Uploaded on: December 4, 2022 -
June 28, 2019 (v1)Publication
Mobile devices, at each new release of the standards and following users' continuous requests of new services, have to support more and more features, which are also becoming more and more demanding from the computational point of view. As a consequence, being able to fulfil new requirements and at the same time to provide power efficient chips...
Uploaded on: December 4, 2022 -
December 5, 2017 (v1)Conference paper
Power management is a key feature in many digital systems, mainly those powered by battery. Introducing a power management strategy in a system should save power consumption while its functional performance must remain within application-dependent constraints. Designing such systems could be very challenging since power management impacts...
Uploaded on: February 28, 2023 -
October 27, 2020 (v1)Conference paper
The semiconductor industry is developing smaller transistors and succeeding in increasing their on-chip integration density. Therefore, the computing power of modern Integrated Circuits (IC) is constantly increasing and their application domains are becoming countless. However, the increasing complexity leads to higher power consumption and...
Uploaded on: December 4, 2022 -
July 6, 2016 (v1)Conference paper
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design...
Uploaded on: February 28, 2023 -
September 14, 2015 (v1)Conference paper
Designing power efficient systems requires both the right low power SoC architecture and the appropriate power management software. Designer/developer teams need to address this requirement as early as possible in the development cycle. Electronic System Level (ESL) tools and methods for virtual prototyping are ...
Uploaded on: February 28, 2023 -
June 14, 2017 (v1)Conference paper
System-on-Chip (SoC) designers face many challenges to improve at the same time performance and energy efficiency, due to the continuous increase of the architecture complexity. Designers use Electronic System Level (ESL) tools and virtual prototyping to face this complexity in the early step of the system design. Power consumption includes...
Uploaded on: February 28, 2023 -
September 3, 2018 (v1)Conference paper
The innovation pace of the wireless communication world is breathtaking, not only due to the fierce competition, but also due to the yearly cadence with which standards bodies deliver a new set of functionalities and services to be supported. In this very dynamic context, optimizing products and differentiate against the competitors is key for...
Uploaded on: December 4, 2022